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CY29973
3.3V 125-MHz Multi-Output Zero Delay Buffer
Features

Output Frequency up to 125 MHz 12 Clock Outputs: Frequency Configurable 350 ps max. Output to Output Skew Configurable Output Disable Two Reference Clock Inputs for Dynamic Toggling Oscillator or PECL Reference Input

Spread Spectrum Compatible Glitch-free Output Clocks Transitioning 3.3V Power Supply Pin Compatible with MPC973 Industrial Temperature Range: - 40C to +85C 52-Pin TQFP Package
Table 1. Frequency Table[1] VC0_SEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FB_SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FB_SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FB_SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FVC0 8x 12x 16x 20x 16x 24x 32x 40x 4x 6x 8x 10x 8x 12x 16x 20x
Note 1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz.
Cypress Semiconductor Corporation Document #: 38-07291 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 09, 2008
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CY29973
Logic Block Diagram
PECL_CLK PECL_CLK# VCO_SEL PLL_EN REF_SEL DQ TCLK0 TCLK1 TCLK_SEL FB_IN DQ Sync Frz 0 1 Phase Detector LPF VCO 0 1 Sync Frz QA0 QA1 QA2 QA3 QB0 QB1 FB_SEL2 QB2 QB3
MR#/OE Power-On Reset SELA(0,1) SELB(0,1) SELC(0,1) FB_SEL(0,1) SCLK SDATA INV_CLK Output Disable Circuitry 12 2 2 2 2 /4, /6, /8, /10 Sync Pulse Data Generator DQ /2 0 1 DQ DQ /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 DQ
Sync Frz
QC0 QC1
Sync Frz Sync Frz Sync Frz
QC2 QC3 FB_OUT
SYNC
Pinouts
SELB1 SELB0 SELA1 SELA0 QA3 VDDC QA2 VSS QA1 VDDC QA0 VSS VCO_SEL 52 51 50 49 48 47 46 45 44 43 42 41 40 VSS MR#/OE SCLK SDATA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 PECL_CLK PECL_CLK# VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 VSS QB0 VDDC QB1 VSS QB2 VDDC QB3 FB_IN VSS FB_OUT VDDC FB_SEL0
CY29973
14 15 16 17 18 19 20 21 22 23 24 25 26 FB_SEL1 SYNC VSS QC0 VDDC QC1 SELC0 SELC1 QC2 VDDC QC3 VSS INV_CLK
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CY29973
Pin Definitions[2]
Pin 11 12 9 10 Name PECL_CLK PECL_CLK# TCLK0 TCLK1 VDDC VDDC VDDC VDDC PWR IO I I I I O O O O Type PU PD PU PU PECL Clock Input. PECL Clock Input. External Reference or Test Clock Input. External Reference or Test Clock Input. Clock Outputs. See Table 2 on page 4 for frequency selections. Clock Outputs. See Table 2 on page 4 for frequency selections. Clock Outputs. See Table 2 on page 4 for frequency selections. Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL(0:2). See Table 1 on page 1. A bypass delay capacitor at this output control Input Reference or Output Banks phase relationships. Synchronous Pulse Output. This output is used for system synchronization. The rising edge of the output pulse is in sync with both the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios selected. PU PU PU PU PU PU PU PU PU PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3) outputs. See Table 2 on page 4. Frequency Select Inputs. These inputs select the divider ratio at QB(0:3) outputs. See Table 2 on page 4. Frequency Select Inputs. These inputs select the divider ratio at QC(0:3) outputs. See Table 2 on page 4. Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1 on page 1. VCO Divider Select Input. When set LOW, the VCO output is divided by 2. When set HIGH, the divider is bypassed. See Table 1 on page 1. Feedback Clock Input. Connect to FB_OUT for accessing the PLL. PLL Enable Input. When asserted HIGH, PLL is enabled. When LOW, PLL is bypassed. Reference Select Input. When HIGH, the PECL inputs are selected. When LOW, TCLK[0:1] are selected. TCLK Select Input. When LOW, TCLK0 is selected. When HIGH TCLK1 is selected. Master Reset or Output Enable Input. When asserted LOW, resets all of the internal flip-flops and also disables all of the outputs. When pulled HIGH, releases the internal flip-flops from reset and enables all of the outputs. Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When set LOW, the inverter is bypassed. Serial Clock Input. Clocks data at SDATA into the internal register. Serial Data Input. Input data is clocked to the internal register to enable or disable individual outputs. This provides flexibility in power management. 3.3V Power Supply for Output Clock Buffers. 3.3V Supply for PLL. Common Ground. Description
44, 46, 48, 50 QA(3:0) 32, 34, 36, 38 QB(3:0) 16, 18, 21, 23 QC(3:0) 29 FB_OUT
25
SYNC
VDDC
O
42, 43 40, 41 19, 20 5, 26, 27 52 31 6 7 8 2
SELA(1,0) SELB(1,0) SELC(1,0) FB_SEL(2:0) VCO_SEL FB_IN PLL_EN REF_SEL TCLK_SEL MR#/OE
I I I I I I I I I I
14 3 4 17, 22, 28, 33,37, 45, 49 13
INV_CLK SCLK SDATA VDDC VDD
I I I
PU PU PU
1, 15, 24, 30, VSS 35, 39, 47, 51
Note 2. A bypass capacitor (0.1F) must be placed as close as possible to each positive power (<0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristics is cancelled by the lead inductance of the traces.
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CY29973
Description
The CY29973 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs and an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125 MHz. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs, refer to Table 1 on page 1. The VCO frequency is then divided down to provide the required output frequencies. These dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs, see Table 2. For situations were the VCO needs to run at relatively low frequencies and hence might not be stable, assert VCO_SEL LOW to divide the VCO frequency by 2. This maintains the desired output relationships, but provides an enhanced PLL lock range. The CY29973 is also capable of providing inverted output clocks. When INV_CLK is asserted high, QC2 and QC3 output clocks are inverted. These clocks could be used as feedback outputs to the CY29973 or a second PLL device to generate early or late clocks for a specific design. This inversion does not affect the output to output skew.
Zero Delay Buffer
When used as a zero delay buffer the CY29973 is likely to be in a nested clock tree application. For these applications the CY29973 offers a low voltage PECL clock input as a PLL reference. This allows the user to use LVPECL as the primary clock distribution device to take advantage of its far superior skew performance. The CY29973 then can lock onto the LVPECL reference and translate with near zero delay to low skew outputs. By using one of the outputs as a feedback to the PLL the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. Because the static phase offset is a function of the reference clock the Tpd of the CY29973 is a function of the configuration used.
Glitch-Free Output Frequency Transitions
Customarily when output buffers have their internal counter's changed "on the fly' their output clock periods will: 1. Contain short or "runt" clock periods. These are clock cycles in which the cycle(s) are shorter in period than either the old or new frequency that is being transitioned to. 2. Contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old or new frequency that is being transitioned to. This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic levels of any or all of the following pins changed "on the fly" while it is operating: SELA, SELB, SELC, and VCO_SEL.
Table 2. Divider Table VCO_SEL 0 0 0 0 1 1 1 1 SELA1 0 0 1 1 0 0 1 1 SELA0 0 1 0 1 0 1 0 1 QA VCO/8 VCO/12 VCO/16 VCO/24 VCO/4 VCO/6 VCO/8 VCO/12 SELB1 0 0 1 1 0 0 1 1 SELB0 0 1 0 1 0 1 0 1 QB VCO/8 VCO/12 VCO/16 VCO/20 VCO/4 VCO/6 VCO/8 VCO/10 SELC1 0 0 1 1 0 0 1 1 SELC0 0 1 0 1 0 1 0 1 QC VCO/4 VCO/8 VCO/12 VCO/16 VCO/2 VCO/4 VCO/6 VCO/8
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CY29973
SYNC Output
In situations were output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system synchronization. The CY29973 monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for the SYNC output. Note that the SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal. Figure 1. SYNC Output for Different Input and Out Ratio
VCO 1:1 Mode QA QC SYNC 2:1 Mode QA QC SYNC 3:1 Mode QC QA SYNC 3:2 Mode QA QC SYNC 4:1 Mode QC QA SYNC 4:3 Mode QA QC SYNC 6:1 Mode QA QC SYNC
Document #: 38-07291 Rev. *C
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CY29973
Power Management
The individual output enable or freeze control of the CY29973 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic `0' state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks. The QC0 and FB_OUT outputs can not be frozen with the serial port, this avoids any potential lock up situation must an error occur in the loading of the serial data. An output is frozen when a logic `0' is programmed and enabled when a logic `1' is written. The enabling and freezing of individual outputs is done in such a manner as to eliminate the possibility of partial "runt" clocks. The serial input register is programmed through the SDATA input by writing a logic `0' start bit followed by 12 NRZ freeze enable bits. The period of each SDATA bit equals the period of the free running SCLK signal. The SDATA is sampled on the rising edge of SCLK. Figure 2. Control Bit Map
Start Bit D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
D0-D3 are the control bits for QA0-QA3, respectively D4-D7 are the control bits for QB0-QB3, respectively D8-D10 are the control bits for QC1-QC3, respectively D11 is the control bit for SYNC
Absolute Maximum Conditions[3]
Maximum Input Voltage Relative to VSS:.............. VSS - 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ - 65C to + 150C Operating Temperature:................................ - 40C to +85C Maximum ESD protection............................................... 2 kV Maximum Power Supply:................................................ 5.5V Maximum Input Current:................................................ 20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions must be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout must be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD).
DC Electrical Specifications VDD = 2.9V to 3.6V, VDDC = 3.3V 10%, TA = - 40C to +85C
Parameter VIL VIH VPP VCMR IIL IIH VOL VOH IDDQ IDDA Description Input Low Voltage Input High Voltage Peak-to-Peak Input Voltage PECL_CLK Common Mode Range PECL_CLK[4] Input Low Input High Current[5] Current[5] Voltage[6] Voltage[6] IOL = 20 mA IOH = -20 mA VDD only Conditions Min VSS 2.0 300 VDD - 2.0 - - - 2.4 - - Typ. - - - - - - - - 10 15 Max 0.8 VDD 1000 VDD - 0.6 -120 120 0.5 - 15 20 Unit V V mV V A A V V mA mA
Output Low Output High
Quiescent Supply Current PLL Supply Current
Notes 3. Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the "High" input is within the VCMR range and the input lies within the VPP specification. 5. Inputs have pull up/pull down resistors that effect input current. 6. Driving series or parallel terminated 50 (or 50 to VDD/2) transmission lines.
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CY29973
DC Electrical Specifications VDD = 2.9V to 3.6V, VDDC = 3.3V 10%, TA = - 40C to +85C
Parameter IDD Description Dynamic Supply Current Conditions QA and QB at 60 MHz, QC at 120 MHz, CL=30 pF QA and QB at 25 MHz, QC at 50 MHz, CL=30 pF Cin ZOUT Input Pin Capacitance Output Impedance Min - - - 15
(continued) Typ. 225 125 4 18 Max - - - 22 pF Unit mA
AC Electrical Specifications VDD = 2.9V to 3.6V, VDDC = 3.3V 10%, TA = - 40C to +85C [7]
Parameter Tr/Tf Fref FrefDC Fvco Tlock Tr/Tf Fout Description TCLK Input Rise or Fall Reference Input Frequency Reference Input Duty Cycle PLL VCO Lock Range Maximum PLL lock Time Output Clocks Rise or Fall Time[9] 0.8V to 2.0V Q (/2) Q (/4) Q (/6) Q (/8) FoutDC tpZL, tpZH tpLZ, tpHZ TCCJ TSKEW Tpd Output Duty Cycle[9] Time[9](all Time[9](all outputs) outputs) to peak) Skew[9,10] QFB =(8) Output Enable Output Disable Cycle to Cycle Maximum Output Frequency Note 8 25 200 - 0.15 - - - - TCYCLE/2 - 750 2 2 - - - 225 - 70 - 130 Conditions Min Typ. - - - - - - - - - - - - - 100 250 - 25 130 70 Max 3.0 Note 8 75 480 10 1.2 125 120 80 60 TCYCLE/2 + 750 10 8 - 350 175 330 270 ps ns ns ps ps ps Unit ns MHz % MHz ms ns MHz
Jitter[9](peak
Any Output to Any Output
Propagation Delay[10,11] PECL_CLK TCLK0 TCLK1
Ordering Information
Part Number CY29973AI[12] CY29973AIT[12] Pb-Free CY29973AXI CY29973AXIT 52-pin TQFP 52-pin TQFP - Tape and reel Industrial, - 40C to +85C Industrial, - 40C to +85C Package Type 52-pin TQFP 52-pin TQFP- Tape and reel Production Flow Industrial, - 40C to +85C Industrial, - 40C to +85C
Notes 7. Parameters are guaranteed by design and characterization. Not 100% tested in production. 8. Maximum and minimum input reference is limited by VC0 lock range. 9. Outputs loaded with 30pF each. 10. 50 transmission line terminated into VDD/2. 11. Tpd is specified for a 50MHz input reference. Tpd does not include jitter. 12. Not recommended for new designs.
Document #: 38-07291 Rev. *C
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CY29973
Package Drawing and Dimensions
Figure 3. 52-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B
51-85158-**
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CY29973
Document History Page
Document Title: CY29973 3.3V 125-MHz Multi-Output Zero Delay Buffer Document Number: 38-07291 REV. ** *A *B *C ECN 111102 122883 200081 2562606 Orig. of Change BRK RBI RGL AESA Submission Date 02/07/02 12/22/02 01/22/04 09/09/08 New data sheet Added power up requirements to Maximum Ratings Added ZOUT specifications in the DC Electrical Specs Changed the Package Drawing and Dimension to CY standard Updated template. Added Note "Not recommended for new designs." Added part number CY29973AXI and CY29973AXIT in ordering information table. Description of Change
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(c) Cypress Semiconductor Corporation, 2002 - 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07291 Rev. *C
Revised September 09, 2008
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